81 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			Markdown
		
	
	
	
	
	
			
		
		
	
	
			81 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			Markdown
		
	
	
	
	
	
| up:: [[Logique séquentielle]]
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| #s/informatique #s/maths/logique 
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| 
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| # ALU binary operators
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| 
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| | bin | operator   |
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| | ---:|:---------- |
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| | 000 | COMParison |
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| | 001 | zero       |
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| | 010 | OR         |
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| | 011 | AND        |
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| | 100 | ADD (+)    |
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| | 101 | SUB (-)    |
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| | 110 | COPY A     |
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| | 111 | COPY B     |
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| 
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| # How to operate
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| 
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| ## op exec
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| 
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| `op exec` is the component that gathers the ALU and the data registers. It can :
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| 
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| - perform operations with the ALU
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| - read data : register to ALU inputs
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| - write data : ALU output to registers
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| - take input : 8 bit bus to ALU inputs
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| - give output : ALU output or registers to 8 bit bus
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| 
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| 
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| > [!info] Writing data to a register
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| > It is not possible to write data directly from the 8 bit bus to the registers.
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| > If you want to register some data, you have to do the following :
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| >  - write the data to the ALU inputs (input A for example)
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| >  - set the ALU operation to copy (copy A in our example, that is `110`)
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| >  - write from the alu to the register (give the register address in the 8 bit bus, and set the `from ALU` and `to register` bits)
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| 
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| 
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| 
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| # Binary code
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| The binary code of the CPU. They are stored in 2 octets.
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| 
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| |            binary code | action          |
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| | ----------------------:| --------------- |
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| | `0000 0000  0000 0000` | NOOP            |
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| |     SET ALU OPERATIONS |                 |
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| | `XXX0 0000  0000 0001` | set X as ALU op |
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| | `0000 0000  0000 0001` | COMParison      |
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| | `0001 0000  0000 0001` | ZERO            |
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| | `0010 0000  0000 0001` | OR              |
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| | `0011 0000  0000 0001` | AND             |
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| | `0100 0000  0000 0001` | A+B             |
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| | `0101 0000  0000 0001` | A-B             |
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| | `0110 0000  0000 0001` | BYPASS A        |
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| | `0111 0000  0000 0001` | BYPASS B        |
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| |           READ / WRITE |                 |
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| | `XXXX XXXX  0000 0010` | X --> ALU A     |
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| | `XXXX XXXX  0000 0011` | X --> ALU B     |
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| | `XXXX XXXX  0000 0110` | reg X --> ALU A |
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| | `XXXX XXXX  0000 0111` | reg X --> ALU B |
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| | `0000 0000  0000 1000` | ALU --> reg     |
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| 
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| ![[digital logic sim computer 2023-07-18 09.57.52.excalidraw]]
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| 
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| | bin | operator   |
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| | ---:|:---------- |
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| | 000 | COMParison |
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| | 001 | zero       |
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| | 010 | OR         |
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| | 011 | AND        |
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| | 100 | ADD (+)    |
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| | 101 | SUB (-)    |
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| | 110 | COPY A     |
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| | 111 | COPY B     |
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| 
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| 
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| write 10 to A -> 0001010 00000100
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| write 11 to B -> 0001011 00001000
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| write 100 to op 00000100 00010000
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